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| tm TE CH Preliminary T15V4M16A SRAM FEATURES * Low-power consumption - Active: 5mA (ICC1 ) - Stand-by: 10uA (CMOS input/output) * 55/70/100 ns access time * Equal access and cycle time * Single +2.7V to 3.6V Power Supply * TTL compatible , Tri-sta te output * Common I/O capability * Automatic power-down when deselected * Available in 44-PIN TSOP-II and 48-pin CSP packages 256K X 16 LOW POWER CMOS STATIC RAM GENERAL DESCRIPTION The T15V4M16A is a very Low Power CMOS Static RAM organized as 262,144 words by 16 bits. That operates on a wide voltage range from 2.7V to 3.6V power supply, Fabricated using high performance CMOS technology, Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Data retention is guaranteed at a power supply voltage as low as 1.5V. BLOCK DIAGRAM PART NUMBER EXAMPLES PART NO. T15V4M16A-55S T15V4M16A-70C T15V4M16A-100C PACKAGE CODE S = TSOP-II C = CSP Vcc Vss A0 . . . DECODER CORE ARRAY A17 CE WE OE LB UB CONTROL CIRCUIT DATA I/O I/O1 . . . I/O16 Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. P. 1 Publication Date: SEP. 2000 Revision:0.B tm A4 A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A16 A15 A14 A13 A12 TE CH Preliminary T15V4M16A A5 A6 A7 OE UB LB I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 A17 PIN CONFIGURATIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 TSOP-II 1 A B C D E F G H LB 2 OE 3 A0 4 A1 5 A2 6 NC I/O9 UB A3 A4 CE I/O1 I/O10 I/O11 A5 A6 I/O2 I/O3 VSS I/O12 A17 A7 I/O4 VCC VCC I/O13 NC A16 I/O5 VSS I/O15 I/O14 A14 A15 I/O6 I/O7 I/O16 NC A12 A13 WE I/O8 NC A8 A9 A10 A11 NC 48-Ball CSP TOP VIEW (Ball Down) PIN DESCRIPTIONS SYMBOL DESCRIPTIONS A0 ~ A17 CE SYMBOL DESCRIPTIONS LB Address inputs Chip enable Write enable input Output enable input Lower byte (I/O 1~8) Upper byte (I/O 9~16) Power supply Ground No connection P. 2 Publication Date: SEP. 2000 Revision:0.B I/O1~I/O16 Data inputs/outputs WE OE UB VCC VSS NC Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. tm TE CH Preliminary T15V4M16A ABSOLUTE MAXIMUM RATINGS* PARAMETER Voltage on Any Pin Relative to VSS Power Dissipation Storage Temperature Temperature Under Bias SYM VR PD T STG IBIAS MIN. -0.2 -55 -40 MAX. +3.6 V 1.0 +150 +85 UNIT V W C C *Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and function operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. TRUTH TABLE OE WE CE H X* X* X* X* X* L H H L H H L L H L L H L L H L X* L L X* L L X* L *Note: X = Don't Care LB UB I/O 1~8 I/O 9~16 MODE Power X* X* High-Z High-Z Deselected H H High-Z High-Z Deselected L X* High-Z High-Z Output Disabled X* L High-Z High-Z Output Disabled L H Data Out High-Z Lower Byte Read H L High-Z Data Out Upper Byte Read L L Data Out Data Out Word Read L H Data In High-Z Lower Byte Write H L High-Z Data In Upper Byte Write L L Data In Data In Word Write (Must be low or high state), L = Low, H = High Standby Standby Active Active Active Active Active Active Active Active Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. P. 3 Publication Date: SEP. 2000 Revision:0.B tm TE CH Preliminary T15V4M16A RECOMMENDED OPERATING CONDITIONS (Ta = -40C to 85C**) PARAMETER Supply Voltage Input Voltage SYM Vcc VSS MIN 2.7 0.0 2.1 -0.2 TYP 3.0 0.0 MAX 3.6 0.0 Vcc+0.3 0.6 UNIT V V V V VIH VIL OPERATING CHARACTERISTICS (Vcc = 2.7 to 3.6V, V SS = 0V, Ta = -40C to 85C) PARAMETER Input Leakage Current Output Leakage Current SYM. TEST CONDITIONS -55 Min Max -70 Min Max -100 Min Max UNIT uA ILI Vcc = Max, VIN = VSS to Vcc - 1 - 1 - 1 CE = VIH or OE = V IH ILO or WE = V IL VIO = VSS to Vcc CE = VIL, WE =VIH, OE = VIH , Operating Power ICC Supply Current VIN = VIH or VIL, IOUT=0mA Cycle time=1us, 100% duty, IIO=0mA, ICC1 CE 0.2V, VIN VCC-0.2V Average Operating or VIN 0.2V Current Cycle time=min, 100% duty, IIO=0mA, ICC2 CE = VIL, VIN = VIH or VIL CE =VIH or Standby Power IS B LB = UB = VIH Supply Current (TTL Level) other input= V IL or VIH CE Vcc-0.2V or Standby Power LB = UB Vcc-0.2V, IS B1 Supply Current VIN 0.2V or (CMOS Level) VIN Vcc-0.2V VOL I OL = 2.1mA Output Low Voltage Output High Voltage VOH I OH = -1.0 mA Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. - 1 - 1 - 1 uA - 3 - 3 - 3 mA - 5 - 5 - 5 mA - 45 - 40 - 30 mA - 0.3 - 0.3 - 0.3 mA - 10 - 10 - 10 uA 2.2 0.4 - 2.2 0.4 - 2.2 0.4 - V V P. 4 Publication Date: SEP. 2000 Revision:0.B tm TE CH Preliminary T15V4M16A CAPACITANCE (f = 1 MHz, Ta = 25C,) PARAMETER Input Capacitance Input/ Output Capacitance SYMBOL CONDITION VIN = 0V VIN = VOUT= 0V MAX. 8 10 UNIT pF pF CIN CI /O Note: This parameter is guaranteed by device characterization and is not production tested. AC TEST CONDITIONS PARAMETER Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Leve l Output Load CONDITIONS 0.6V to 2.1V 3.0 ns 1.4V C L =30pF+1TTL Load(55ns/70ns) C L =100pF+1TTL Load(Load for 100ns) AC TEST LOADS AND WAVEFORM TTL DQ RL 50 ohm CL 30 pF CL* Z0 = 50 ohm Vt =1.4V Fig.A * Including Scope and Jig Capacitance Fig.B Output Load Equivalent Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. P. 5 Publication Date: SEP. 2000 Revision:0.B tm TE CH Preliminary T15V4M16A VSS = 0V, Ta = -40C to 85C) AC CHARACTERISTICS(Vcc =2.7 to 3.6V, (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Output Hold from Address Change Chip Enable to Output in Low -Z Chip Disable to Output in High-Z Output Enable to Output in Low-Z Output Disable to Output in High-Z LB , UB Access Time LB , UB Enable to Output in Low-Z LB , UB Disable to Output in High-Z SYM. tRC tAA tACE tOE tOH tLZ tHZ tOLZ tOHZ tBA tBLZ tBHZ -55 Min Max Min -70 Max -100 Min Max UNIT ns ns ns ns ns ns ns ns ns ns ns ns 55 10 10 5 10 - 55 55 30 20 20 55 20 70 10 10 5 10 - 70 70 35 25 25 70 25 100 10 10 5 10 - 100 100 50 30 30 100 30 (2)WRITE CYCLE PARAMETER Write Cycle Time Chip Enable to Write End Address Valid to Write End Address Setup Time Write Pulse Width Write Recovery Time Data Valid to Write End Data Hold Time Write Enable to Output in High-Z Output Active from Write End SYM. tWC tCW tAW tAS tWP tWR tDW tDH tWHZ tOW -55 Min Max Min -70 Max -100 Min Max UNIT ns ns ns ns ns ns ns ns ns ns 55 50 50 0 45 0 25 0 5 20 - 70 60 60 0 50 0 30 0 5 25 - 100 80 80 0 70 0 40 0 5 30 - Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. P. 6 Publication Date: SEP. 2000 Revision:0.B tm TE CH Preliminary T15V4M16A TIMING WAVEFORMS READ CYCLE 1 (Address Controlled, CE = OE = VIL , WE = VIH , LB or/and UB = VIL ) tRC Ad dr es s t AA t OH D OUT Previous Data Valid Data Valid READ CYCLE 2 ( WE = VIH) tR C Address tA A CE t OH t HZ tA C E tB A UB / LB t OE OE tB H Z t LZ D OUT tB LZ tOLZ t OH Z High-Z DON'T CARE UNDEFINED (Chip Enable Controlled) Notes (READ CYCLE) : 1. WE are high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZand t OHZ are defined as the time at which the outputs achieve the open circuit condition referenced to VOH or VOL levels. 4. At any given temperature and voltage condition. tHZ (max.) is less than tLZ (min.) both for a given device and from device to device interconnection. 5. Transition is measured 200mV from steady state voltage with load. This parameter is sampled and not 100% tested. 6. Device is continuously selected with CE =VIL . Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. P. 7 Publication Date: SEP. 2000 Revision:0.B tm Add r es s CE TE CH Preliminary T15V4M16A tWC WRITE CYCLE 1 ( WE Controlled) t AW t CW t W R UB / LB tAS tW P WE tW HZ t OW DO UT High-Z tDW tDH DI N Hig h - Z WRITE CYCLE 2 ( CE Controlled) Ad d r ess tAW tW C tWR tCW CE t AS UB / LB t W P WE DOUT High-Z tDW tDH DIN High-Z H ig h -Z DO N 'T C AR E UN D EF INE D Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. P. 8 Publication Date: SEP. 2000 Revision:0.B tm A dd re s s TE CH Preliminary T15V4M16A WRITE CYCLE 3 ( UB , LB Controlled) t W C t AW t CW t WR UB / LB t AS CE tWP WE DOUT High-Z tDW tDH DIN High-Z High-Z DO N 'T C AR E UN D EF INE D NOTES ( WRITE CYCLE ) : 1. A write occurs during the overlap of a low CE , a low WE . A write begins at the lateat transition among CE goes low, WE going low. A write end at the earliest transition among CE going high, WE going high. tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the later of CE going low to the end of write. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. 3. Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. P. 9 Publication Date: SEP. 2000 Revision:0.B tm TE CH Preliminary T15V4M16A DATA RETENTION CHARACTERISTICS PARAMETER VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time SYM. VDR ICCDR tCDR tR TEST CONDITION CE VCC -0.2V VIN Vcc -0.2V or VIN 0.2V MIN. 1.5 0 RC t MAX. 10 UNIT V uA ns ns DATA RETENTION WAVEFORM (Ta = -40C to 85C) D ata R ete nti o n M o de V cc _ty p tR Vcc V c c_ ty p tC D R V D R > 1 .5 V CE V IH C E >V c c- 0 . 2 V V IH Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. P. 10 Publication Date: SEP. 2000 Revision:0.B tm TE CH Preliminary T15V4M16A PACKAGE DIMENSIONS 44-LEAD TSOP-II D 44 23 E E1 E2 L1 INDEX MARK Mirror finish c e b A c A2 c1 SEATING PLANE A1 A3 L 22 b1 Symbol A A1 A2 A3 b b1 c c1 D e E E1 E2 L L1 Dimension in mm Min Nom Max 1.20 0.05 0.1 0.95 1.00 1.05 0.25 0.35(typ) 0.10 0. 15 0.25 0.805 0.10 18.31 18.41 18.51 0.80(typ) 11.56 11.76 11.96 10.03 10.16 10.29 10.76 0.4 0.5 0.6 0.8(typ) 0 8 Dimension in inch Min Nom Max 0.047 0.002 0.004 0.037 0.039 0.041 0.010 0.014(typ) 0.004 0.006 0.010 0.032 0.004 0.721 0.725 0.729 0.031(typ) 0.455 0.463 0.471 0.394 0.400 0.405 0.458 0.016 0.020 0.024 0.032(typ) 0 8 Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. P. 11 Publication Date: SEP. 2000 Revision:0.B tm TE CH Preliminary T15V4M16A Units : millimeters PACKAGE DIMENSIONS 48-pin CSP (8 row x 6 column) 48 BALL FINE PITCH BGA (0.75mm ball pitch) Top V iew Bottom View B B1 A1 INDEX MARK 0. 50 0 .5 0 #A1 C C1 C1/2 B /2 A E2 Y D 0.30 E E1 Symbol A B B1 C C1 D E E1 E2 Y min 5.95 7.95 0.25 0.20 - typ 0.75 6.00 3.75 8.00 5.25 0.30 1.10 0.95 0.25 - max 6.05 8.05 0.35 1.20 0.30 0.08 P. 12 Publication Date: SEP. 2000 Revision:0.B Notes : 1. Bump counts : 48 (8 row x 6column) 2. Bump pitch : (x,y)=(0.75 x 0.75) typ. 3. All tolerance are 0.050 unless otherwise specified. 4. `Y' is coplanarity : 0.08(max) 5. Units : mm Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. |
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